Download Computing with Memory for Energy-Efficient Robust Systems by Somnath Paul PDF

By Somnath Paul

This ebook analyzes power and reliability as significant demanding situations confronted by way of designers of computing frameworks within the nanometer know-how regime. The authors describe the prevailing recommendations to handle those demanding situations after which demonstrate a brand new reconfigurable computing platform, which leverages high-density nanoscale reminiscence for either info garage and computation to maximise the energy-efficiency and reliability. The power and reliability merits of this new paradigm are illustrated and the layout demanding situations are mentioned. a variety of and software program elements of this interesting computing paradigm are defined, relatively with admire to hardware-software co-designed frameworks, the place the unit should be reconfigured to imitate different software habit. eventually, the energy-efficiency of the paradigm defined is in comparison with different, famous reconfigurable computing platforms.

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Brunelli, F. Garzia, J. Nurmi, “A coarse-grain reconfigurable architecture for multimedia applications featuring subword computation capabilities”. J. Real Time Image Process. 3(1), 21–32 (2006) 14. [Online], “The Kress ALU Array”. html 15. R. D. Smith, “A High-Performance Microarchitecture with HardwareProgrammable Functional Units”, in Intl. Symp. on Microarchitecture, 1994 16. T. Miyamori, K. Olukotun, “REMARC: Reconfigurable Multimedia Array Coprocessor”, in Intl. Symp. on FPGAs, 1998 17. D.

3 Challenges in Reconfigurable Hardware Design As technology scales reconfigurable systems are confronted by a number of challenges at all levels of design abstraction, namely, circuit, architecture and software. The common challenges which applies to all three are (i) minimizing the power for reconfigurable frameworks, (ii) improving the performance of the reconfigurable framework and (iii) tolerate defects. Here we try to summarize the solutions which have been proposed to address these challenges.

IEEE Trans. Comput. Aided Des. Integrat. Circ. Syst. 19(11), 1268–1281 (2000) 5. S. Trimberger, “Scheduling Designs into a Time-Multiplexed FPGA”, in Intl. Symp. on FPGAs, 1998 6. D. M. Lewis, “Time-Multiplexed FPGA Architecture for Logic Evaluation”, in Custom Integrated Circuits Conference, 1995 7. A. Dehon, “DPGA Utilization and Application”, in Intl. Symp. on FPGAs, 1996 8. G. Wu, J. Land, Y. Chang, “Generic ILP-based approaches for time-multiplexed FPGA partitioning”. IEEE Trans. Comput. Aided Des.

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